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1 lt1575/lt1577 ultrafast transient response, low dropout regulators adjustable and fixed typical applicatio n u 1 2 3 4 8 7 6 5 shdn v in gnd out ipos ineg gate comp c2 1 m f c5 220 m f 5v gnd 1575/77 ta01 v out 3.3v 5a r2 5 w r1 7.5k 12v lt1575-3.3 c4 1000pf for t > 45 c: c6 = 24 1 m f x7r ceramic surface mount capacitors. place c6 in the microprocessor socket cavity for t < 45 c: c6 = 24 1 m f y5v ceramic surface mount capacitors. * q1 irfz24 + c3 10pf c6* 24 m f ultrafast transient response 5v to 3.3v low dropout regulator (for schematic including current limit, see typical applications) 50mv/div 2a/div 100 m s/div 1575/77 ta02 transient response for 0.2a to 5a output load step n pentium ? processor supplies n powerpc tm supplies n 5v to 3.xxv or 3.3v to 2.xxv microprocessor supplies n gtl termination n low voltage logic supplies lt1575cn8/lt1575cs8 adjustable lt1575cn8-1.5/lt1575cs8-1.5 1.5v fixed lt1575cn8-2.8/lt1575cs8-2.8 2.8v fixed lt1575cn8-3.3/lt1575cs8-3.3 3.3v fixed lt1575cn8-3.5/lt1575cs8-3.5 3.5v fixed lt1575cn8-5/lt1575cs8-5 5v fixed lt1577cs-adj/adj adjustable, adjustable lt1577cs-3.3/adj 3.3v fixed, adjustable lt1577cs-3.3/2.8 3.3v fixed, 2.8v fixed consult factory for additional output voltage combinations available in the lt1577. applicatio n s u descriptio n u n ultrafast tm transient response eliminates tantalum and electrolytic output capacitors n fet r ds(on) defines dropout voltage n 1% reference/output voltage tolerance over temperature n typical load regulation: 1mv n high side sense current limit n multifunction shutdown pin with latchoff features the lt ? 1575/lt1577 are single/dual controller ics that drive low cost external n-channel mosfets as source followers to produce ultrafast transient response, low dropout voltage regulators. the lt1575/lt1577 achieve unprecedented transient- load performance by eliminating expensive tantalum or bulk electrolytic output capacitors in the most demanding modern microprocessor applications. precision-trimmed adjustable and fixed output voltage versions accommo- date any required microprocessor power supply voltage. selection of the n-channel mosfet r ds(on) allows very low dropout voltages to be achieved. unique protection features include a high side current limit amplifier that activates a fault protection timer circuit. a multifunction shutdown pin provides either current limit time-out with latchoff, overvoltage protec- tion, thermal shutdown or a combination of these func- tions. the lt1575 is available in 8-pin so or pdip and the lt1577 is available in 16-pin narrow body so. ultrafast is a trademark of linear technology corporation. pentium is a registered trademark of intel corporation. powerpc is a trademark of ibm corporation. , ltc and lt are registered trademarks of linear technology corporation.
2 lt1575/lt1577 a u g w a w u w a r b s o lu t exi t i s (note 1) v in , ipos, ineg ...................................................... 22v shdn ....................................................................... v in operating ambient temperature range ..... 0 c to 70 c junction temperature (note 2) ................ 0 c to 100 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c wu u package / o rder i for atio 1 2 3 4 8 7 6 5 top view shdn v in gnd out ipos ineg gate comp s8 package 8-lead plastic so n8 package 8-lead pdip t jmax = 100 c, q ja = 100 c/ w (n8) t jmax = 100 c, q ja = 130 c/ w (s8) lt1575cn8-1.5 lt1575cs8-1.5 lt1575cn8-2.8 lt1575cs8-2.8 lt1575cn8-3.3 order part number order part number lt1575cs8-3.3 lt1575cn8-3.5 lt1575cs8-3.5 lt1575cn8-5 lt1575cs8-5 157535 15755 157515 157528 157533 order part number lt1577cs-adj/adj t jmax = 100 c, q ja = 100 c/ w top view s package 16-lead plastic narrow so 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 shdn1 v in1 gnd1 fb1 shdn2 v in2 gnd2 fb2 ipos1 ineg1 gate1 comp1 ipos2 ineg2 gate2 comp2 1 2 3 4 8 7 6 5 top view shdn v in gnd fb ipos ineg gate comp s8 package 8-lead plastic so n8 package 8-lead pdip t jmax = 100 c, q ja = 100 c/ w (n8) t jmax = 100 c, q ja = 130 c/ w (s8) lt1575cn8 lt1575cs8 1575 s8 part marking s8 part marking consult factory for industrial and military grade parts. order part number lt1577cs-3.3/adj t jmax = 100 c, q ja = 100 c/w top view s package 16-lead plastic narrow so 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 shdn1 v in1 gnd1 out-3.3 shdn2 v in2 gnd2 fb ipos1 ineg1 gate1 comp1 ipos2 ineg2 gate2 comp2 order part number lt1577cs-3.3/2.8 t jmax = 100 c, q ja = 100 c/w top view s package 16-lead plastic narrow so 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 shdn1 v in1 gnd1 out-3.3 shdn2 v in2 gnd2 out-2.8 ipos1 ineg1 gate1 comp1 ipos2 ineg2 gate2 comp2
3 lt1575/lt1577 electrical characteristics t a = 25 c, v in = 12v, gate = 6v, ipos = ineg = 5v, shdn = 0.75v unless otherwise noted. symbol parameter conditions min typ max units i q supply current l 51219 ma v fb lt1575 reference voltage C 0.6 1.210 0.6 % l C 1.0 1.210 1.0 % v out lt1575-1.5 output voltage C 0.6 1.500 0.6 % l C 1.0 1.500 1.0 % lt1575-2.8 output voltage C 0.6 2.800 0.6 % l C 1.0 2.800 1.0 % lt1575-3.3 output voltage C 0.6 3.300 0.6 % l C 1.0 3.300 1.0 % lt1575-3.5 output voltage C 0.6 3.500 0.6 % l C 1.0 3.500 1.0 % lt1575-5 output voltage C 0.6 5.000 0.6 % l C 1.0 5.000 1.0 % line regulation 10v v in 20v l 0.01 0.03 %/v i fb fb input bias current fb = v fb l C 0.6 C 4.0 m a i out out divider current out = v out l 0.5 1.0 1.5 ma a vol lt1575 large-signal voltage gain v gate = 3v to 10v l 69 84 db lt1575-1.5 large-signal voltage gain v gate = 3v to 10v l 67 82 db lt1575-2.8 large-signal voltage gain v gate = 3v to 10v l 60 76 db lt1575-3.3 large-signal voltage gain v gate = 3v to 10v l 60 75 db lt1575-3.5 large-signal voltage gain v gate = 3v to 10v l 60 74 db lt1575-5 large-signal voltage gain v gate = 3v to 10v l 56 71 db v ol gate output swing low (note 3) i gate = 0ma l 2.5 3.0 v v oh gate output swing high i gate = 0ma l v in C 1.6 v in C 1 v ipos + ineg supply current 3v ipos 20v l 0.3 0.625 1.0 ma current limit threshold voltage 42 50 58 mv l 37 50 63 mv current limit threshold voltage 3v ipos 20v l C 0.20 C 0.50 %/v line regulation shdn sink current current flows into pin l 2.5 5.0 8.0 m a shdn source current current flows out of pin l C8 C15 C23 m a shdn low clamp voltage l 0.1 0.25 v shdn high clamp voltage l 1.50 1.85 2.20 v shdn threshold voltage l 1.18 1.21 1.240 v shdn threshold hysteresis l 50 100 150 mv the l denotes specifications which apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: lt1575cn8: t j = t a + (p d ? 100 cw) lt1575cs8: t j = t a + (p d ? 130 cw) lt1577cs: t j = t a + (p d ? 100 cw) because the lt1577 consists of two regulators in the package, the total lt1577 power dissipation must be used for its junction temperature calculation. the total lt1577 p d = p d (regulator 1) + p d (regulator 2). note 3: the v gs(th) of the external mosfet must be greater than 3v C v out .
4 lt1575/lt1577 typical perfor m a n ce characteristics u w quiescent current vs temperature fb input bias current vs temperature adjustable lt1575 v ref vs temperature temperature ( c) ?5 5 quiescent current (ma) 7 9 11 19 15 ?5 25 50 150 17 13 6 8 10 18 14 16 12 ?0 0 75 100 125 175 1575/77 g01 v in = 8v v in = 12v v in = 20v temperature ( c) ?5 reference voltage (v) 1.210 1.214 1.218 1.222 125 1575/77 g02 1.206 1.202 1.208 1.212 1.216 1.220 1.204 1.200 1.198 ?5 25 75 50 150 0 50 100 175 temperature ( c) ?5 fb input bias current ( m a) 3.0 4.0 125 1575/77 g03 2.0 1.0 2.5 3.5 1.5 0.5 0 ?5 25 75 50 150 0 50 100 175 v in = 20v v in = 12v v in = 8v lt1575-3.5 v out vs temperature lt1575-1.5 v out vs temperature lt1575-2.8 v out vs temperature lt1575-3.3 v out vs temperature temperature ( c) ?5 output voltage (v) 3.303 3.315 3.327 3.333 125 1575/77 g06 3.291 3.279 3.297 3.309 3.321 3.285 3.273 3.267 ?5 25 75 ?0 150 0 50 100 175 temperature ( c) ?5 out divider current (ma) 1.1 1.3 1.5 125 1575/77 g09 0.9 0.7 1.0 1.2 1.4 0.8 0.6 0.5 ?5 25 75 50 150 0 50 100 175 out divider current vs temperature temperature ( c) ?5 reference voltage (v) 1.503 1.509 1.515 125 1575/77 g04 1.500 1.497 1.494 1.491 1.488 1.485 1.506 1.512 ?5 25 75 50 150 0 50 100 175 temperature ( c) ?5 output voltage (v) 2.828 ?5 25 50 150 2.824 2.800 2.816 2.812 2.808 2.804 2.800 2.796 2.792 2.788 2.784 2.780 2.776 2.772 ?0 0 75 100 125 175 1575/77 g05 temperature ( c) ?5 output voltage (v) 3.535 ?5 25 50 150 3.530 3.525 3.520 3.515 3.510 3.505 3.500 3.495 3.490 3.485 3.480 3.475 3.470 3.465 ?0 0 75 100 125 175 1575/77 g07 lt1575-5 v out vs temperature temperature ( c) ?5 output voltage (v) 5.010 5.030 5.050 125 1575/77 g08 4.990 4.970 5.000 5.020 5.040 4.980 4.960 4.950 ?5 25 75 ?0 150 0 50 100 175
5 lt1575/lt1577 typical perfor m a n ce characteristics u w error amplifier large-signal voltage gain vs temperature gain and phase vs frequency temperature ( c) 0 line regulation (%/v) 0.010 0.020 0.030 0.005 0.015 0.025 25 25 75 125 1575/77 g10 175 ?0 75 0 50 100 150 v ref /v out line regulation vs temperature temperature ( c) ?5 large-signal voltage gain (db) 105 115 125 1575/77 g11 95 85 100 110 120 90 80 75 70 ?5 25 75 50 150 0 50 100 175 gate output swing high vs temperature ipos + ineg supply current vs temperature temperature ( c) ?5 gate output swing low (v) 2.50 3.00 125 1575/77 g13 2.00 1.50 2.25 2.75 1.75 1.25 1.00 ?5 25 75 50 150 0 50 100 175 i load = 50ma no load gate output swing low vs temperature temperature ( c) 0 gate output swing high (v) 1.0 2.0 3.0 0.5 1.5 2.5 25 25 75 125 1575/77 g14 175 ?0 75 0 50 100 150 no load i load = 50ma temperature ( c) ?5 300 i pos + i neg supply current ( m a) 400 600 700 800 1000 ?0 50 100 1575/77 g15 500 900 25 150 175 ?5 0 75 125 ipos = ineg = 3v ipos = ineg = 5v ipos = ineg = 12v ipos = ineg = 20v frequency (hz) 50 100 error amplifier gain and phase 150 200 1k 100k 1m 100m 1575/77 g12 0 10k 10m phase gain current limit threshold voltage vs temperature temperature ( c) 35 current limit threshold voltage (mv) 45 55 65 40 50 60 25 25 75 125 1575/77 g16 175 ?0 75 0 50 100 150 ipos = 5v ipos = 3v ipos = 20v current limit threshold voltage line regulation vs temperature temperature ( c) ?5 current limit threshold voltage line regulation (%/v) 0.2 0.1 0 125 1575/77 g17 0.3 0.4 0.5 ?5 25 75 50 150 0 50 100 175
6 lt1575/lt1577 typical perfor m a n ce characteristics u w shdn sink current vs temperature temperature ( c) ?5 shdn sink current ( m a) 5.5 6.5 7.5 125 1575/77 g18 4.5 3.5 5.0 6.0 7.0 4.0 3.0 2.5 ?5 25 75 50 150 0 50 100 175 shdn low clamp voltage vs temperature temperature ( c) ?5 shdn low clamp voltage (v) 0.15 0.20 0.25 125 1575/77 g20 0.10 0.05 0 ?5 25 75 50 150 0 50 100 175 shdn source current vs temperature temperature ( c) ?5 shdn source current ( m a) ?5 ?3 ?1 125 1575/77 g19 ?7 ?9 ?6 ?4 ?2 ?8 ?0 ?0 ?5 25 75 50 150 0 50 100 175 shdn hysteresis vs temperature temperature ( c) ?5 shdn hysteresis (mv) 110 130 150 125 1575/77 g22 90 70 100 120 140 80 60 50 ?5 25 75 50 150 0 50 100 175 shdn high clamp voltage vs temperature temperature ( c) 1.5 shdn high clamp voltage (v) 1.7 1.9 2.1 1.6 1.8 2.0 25 25 75 125 1575/77 g21 175 ?0 75 0 50 100 150
7 lt1575/lt1577 pi n fu n ctio n s uuu shdn (pin 1): this is a multifunction shutdown pin that provides gate drive latchoff capability. a 15 m a current source, that turns on when current limit is activated, charges a capacitor placed in series with shdn to gnd and performs a current limit time-out function. the pin is also the input to a comparator referenced to v ref (1.21v). when the pin pulls above v ref , the comparator latches the gate drive to the external mosfet off. the comparator typically has 100mv of hysteresis and the shutdown pin can be pulled low to reset the latchoff function. this pin provides overvoltage protection or thermal shutdown protection when driven from various resistor divider schemes. v in (pin 2): this is the input supply for the ic that powers the majority of internal circuitry and provides sufficient gate drive compliance for the external n-channel mosfet. the typical supply voltage is 12v with 12.5ma of quiescent current. the maximum operating v in is 20v and the minimum operating v in is set by v out + v gs of the mosfet at max. i out + 1.6v (worst-case v in to gate output swing). gnd (pin 3): analog ground. this pin is also the negative sense terminal for the internal 1.21v reference. connect external feedback divider networks that terminate to gnd and frequency compensation components that terminate to gnd directly to this pin for best regulation and perfor- mance. fb (pin 4): this is the inverting input of the error amplifier for the adjustable voltage lt1575. the noninverting input is tied to the internal 1.21v reference. input bias current for this pin is typically 0.6 m a flowing out of the pin. this pin is normally tied to a resistor divider network to set output voltage. tie the top of the external resistor divider directly to the output voltage for best regulation performance. out (pin 4): this is the inverting input of the error amplifier for the fixed voltage lt1575. the fixed voltage parts contain a precision resistor divider network to set output voltage. the typical resistor divider current is 1ma into the pin. tie this pin directly to the output voltage for best regulation performance. comp (pin 5): this is the high impedance gain node of the error amplifier and is used for external frequency compen- sation. the transconductance of the error amplifier is 15 millimhos and open-loop voltage gain is typically 84db. frequency compensation is generally performed with a series rc network to ground. gate (pin 6): this is the output of the error amplifier that drives n-channel mosfets with up to 5000pf of effec- tive gate capacitance. the typical open-loop output impedance is 2 w . when using low input capacitance mosfets (< 1500pf), a small gate resistor of 2 w to 10 w dampens high frequency ringing created by an lc reso- nance that is created by the mosfet gates lead induc- tance and input capacitance. the gate pin delivers up to 50ma for a few hundred nanoseconds when slewing the gate of the n-channel mosfet in response to output load current transients. ineg (pin 7): this is the negative sense terminal of the current limit amplifier. a small sense resistor is connected in series with the drain of the external mosfet and is connected between the ipos and ineg pins. a 50mv threshold voltage in conjunction with the sense resistor value sets the current limit level. the current sense resis- tor can be a low value shunt or can be made from a piece of pc board trace. if the current limit amplifier is not used, tie the ineg pin to ipos to defeat current limit. an alternative is to ground the ineg pin. this action disables the current limit amplifier and additional internal circuitry activates the timer circuit on the shdn pin if the gate pin swings to the v in rail. this option provides the user with a sense-less current limit function. ipos (pin 8): this is the positive sense terminal of the current limit amplifier. tie this pin directly to the main input voltage from which the output voltage is regulated. the typical input voltage is a 5v logic supply. this pin is also the input to a comparator on the fixed voltage ver- sions that monitors the input/output differential voltage of the external mosfet. if this differential voltage is less than 0.5v, then the shdn timer is not allowed to start even if the gate is at the v in rail. this allows the regulator to start up normally as the input voltage is ramping up, even with very slow ramp rates.
8 lt1575/lt1577 block diagra m w lt1575 adjustable voltage sw2 normally closed i2 5 m a + error amp comp 1575/77 bd1 + comp1 q6 shdn v in gnd fb r2 5k sw1 normally open 100mv hysteresis i1 15 m a i3 100 m a + i lim amp v th1 50mv + v th2 1v + d1 ipos ineg gate d2 + comp2 + comp3 or2 start-up v ref 1.21v r1 50k or1 q4 q3 q2 q1 q5
9 lt1575/lt1577 block diagra m w lt1575 fixed voltage sw2 normally closed i2 5 m a + error amp comp 1575/77 bd2 + comp1 q6 shdn v in gnd out r2 5k sw1 normally open 100mv hysteresis i1 15 m a i3 100 m a + i lim amp v th1 50mv + v th3 500mv + v th2 1v + d1 ipos ineg gate d2 + + comp2 comp4 + comp3 or2 start-up v ref 1.21v r1 50k or1 q4 q3 q2 q1 q5 r3* *v out = (1 + r3/r4)v ref r4* q7
10 lt1575/lt1577 applicatio n s i n for m atio n wu u u introduction the current generation of microprocessors place strin- gent demands on the power supply that powers the processor core. these microprocessors cycle load cur- rent from near zero to amps in tens of nanoseconds. output voltage tolerances as low as 100mv include transient response as part of the specification. some microprocessors require only a single output voltage from which the core and i/o circuitry operate. other higher performance processors require a separate power supply voltage for the processor core and the i/o circuitry. these requirements mandate the need for very accurate, very high speed regulator circuits. previously employed solutions included monolithic 3-terminal linear regulators, pnp transistors driven by low cost control circuits and simple buck converter switching regulators. the 3-terminal regulator achieves a high level of integration, the pnp driven regulator achieves very low dropout performance and the switching regulator achieves high electrical efficiency. however, the common trait manifested by these solutions is that transient response is measured in many microsec- onds. this fact translates to a regulator output decoupling capacitor scheme that requires several hundred microfar- ads of very low esr bulk capacitance using multiple capacitors surrounding the cpu. this required bulk ca- pacitance is in addition to the ceramic decoupling capaci- tor network that handles the transient load response during the first few hundred nanoseconds as well as providing microprocessor clock frequency noise immu- nity. the combined cost of all capacitors is a significant percentage of the total power supply cost. the lt1575/lt1577 family of single/dual controller ics are unique, easy to use devices that drive external n-channel mosfets as source followers and permit a user to realize an extremely low dropout, ultrafast transient response regulator. these circuits achieve superior regu- lator bandwidth and transient load performance by com- pletely eliminating expensive tantalum or bulk electrolytic capacitors in the most modern and demanding micropro- cessor applications. for example, a 200mhz pentium processor can operate with only the recommended 24 1 m f ceramic capacitors. users benefit directly by saving sig- nificant cost as all additional bulk capacitance is removed. the additional savings of insertion cost, purchasing/in- ventory cost and board space are readily apparent. precision-trimmed adjustable and fixed output voltage versions accommodate any required microprocessor power supply voltage. proper selection of the n-channel mosfet r ds(on) allows user-settable dropout voltage performance. the only output capacitors required are the high frequency ceramic decoupling capacitors. this regu- lator design provides ample bandwidth and responds to transient load changes in a few hundred nanoseconds versus regulators that respond in many microseconds. the ceramic capacitor network generally consists of 10 to 24 1uf capacitors for individual microprocessor require- ments. the lt1575/lt1577 family also incorporates cur- rent limiting for no additional system cost, provides on/off control and overvoltage protection or thermal shutdown with simple external components. therefore, the unique design of these new ics combines the benefits of low dropout voltage, high functional inte- gration, precision performance and ultrafast transient response, as well as providing significant cost savings on the output capacitance needed in fast load transient appli- cations. as lower input/output differential voltage applica- tions become increasingly prevalent, an lt1575-based solution achieves comparable efficiency performance with a switching regulator at an appreciable cost savings. the new lt1575/lt1577 family of low dropout regulator controller ics step to the next level of performance re- quired by system designers for the latest generation motherboards and microprocessors. the simple versatil- ity and benefits derived from these circuits allow the power supply needs of todays high performance micro- processors to be met with ease. block diagram operation the primary block diagram elements consist of a simple feedback control loop and the secondary block diagram elements consist of multiple protection functions. exam- ining the block diagram for the lt1575, a start-up circuit provides controlled start-up for the ic, including the precision-trimmed bandgap reference, and establishes all internal current and voltage biasing.
11 lt1575/lt1577 applicatio n s i n for m atio n wu u u because the mosfet pass transistor is connected as a source follower, the power path gain is much more pre- dictable than designs that employ a discrete pnp transis- tor as the pass device. this is due to the significant production variations encountered with pnp beta. mosfets are also very high speed devices which enhance the ability to produce a stable wide bandwidth control loop. an additional advantage of the follower topology is inherently good line rejection. input supply disturbances do not propagate through to the output. the feedback loop for a regulator circuit is completed by providing an error signal to the fb pin in the adjustable voltage version and the out pin in the fixed voltage version. in both cases, a resistor divider network senses the output voltage and sets the regulated dc bias point. in general, the lt1575 regulator feedback loop permits a loop crossover fre- quency on the order of 1mhz while maintaining good phase and gain margins. this unity-gain frequency is a factor of 20 to 30 times the bandwidth of currently implemented regulator solutions for microprocessor power supplies. this significant performance benefit is what permits the elimination of all bulk output capacitance. several other unique features are included in the design that increase its functionality and robustness. these func- tions comprise the remainder of the block diagram. a high side sense, current limit amplifier provides active current limiting for the regulator. the current limit ampli- fier uses an external low value shunt resistor connected in series with the external mosfets drain. this resistor can be a discrete shunt resistor or can be manufactured from a kelvin-sensed section of free pc board trace. all load current flows through the mosfet drain and thus, through the sense resistor. the advantage of using high side current sensing in this topology is that the mosfets gain and the main feedback loops gain remain unaffected. the sense resistor develops a voltage equal to i out (r sense ). the current limit amplifiers 50mv threshold voltage is a good compromise between power dissipation in the sense resistor, dropout voltage impact and noise immunity. current limit activates when the sense resistor voltage equals the 50mv threshold. two events occur when current limit activates: the first is that the current limit amplifier drives q2 in the block reference voltage accuracy for the adjustable version and output voltage accuracy for the fixed voltage versions are specified as 0.6% at room temperature and as 1% over the full operating temperature range. this places the lt1575/lt1577 family among a select group of regulators with a very tightly specified output voltage tolerance. the accurate 1.21v reference is tied to the noninverting input of the main error amplifier in the feedback control loop. the error amplifier consists of a single high gain g m stage with a transconductance equal to 15 millimhos. the inverting terminal is brought out as the fb pin in the adjustable voltage version and as the out pin in fixed voltage versions. the g m stage provides differential-to- single ended conversion at the comp pin. the output impedance of the g m stage is about 1m w and thus, 84db of typical dc error amplifier open-loop gain is realized along with a typical 75mhz uncompensated unity-gain crossover frequency. note that the overall feedback loops dc gain decreases from the gain provided by the error amplifier by the attenuation factor in the resistor divider network which sets the dc output voltage. these attenuation factors are already built into the open-loop voltage gain specifications for the lt1575 fixed voltage versions in the electrical characteristics table to simplify user calculations. external access to the high impedance gain node of the error amplifier permits typical loop compensation to be accomplished with a series rc network to ground. a high speed, high current output stage buffers the comp node and drives up to 5000pf of effective mosfet gate capacitance with almost no change in load transient per- formance. the output stage delivers up to 50ma peak when slewing the mosfet gate in response to load current transients. the typical output impedance of the gate pin is typically 2 w . this pushes the pole due to the error amplifier output impedance and the mosfet input capacitance well beyond the loop crossover frequency. if the capacitance of the mosfet used is less than 1500pf, it may be necessary to add a small value series gate resistor of 2 w to 10 w . this gate resistor helps damp the lc resonance created by the mosfet gates lead induc- tance and input capacitance. in addition, the pole formed by this resistance and the mosfet input capacitance can be fine tuned.
12 lt1575/lt1577 applicatio n s i n for m atio n wu u u diagram and clamps the positive swing of the comp node in the main error amplifier to a voltage that provides an output load current of 50mv/r sense . this action contin- ues as long as the output current overload persists. the second event is that a timer circuit activates at the shdn pin. this pin is normally held low by a 5 m a active pull-down that limits to ? 100mv above ground. when current limit activates, the 5 m a pull-down turns off and a 15 m a pull-up current source turns on. placing a capacitor in series with the shdn pin to ground generates a programmable time ramp voltage. the shdn pin is also the positive input of comp1. the negative input is tied to the internal 1.21v reference. when the shdn pin ramps above v ref , the comparator drives q4 and q5. this action pulls the comp and gate pins low and latches the external mosfet drive off. this condition reduces the mosfet power dissipation to zero. the time period until the latched-off condition occurs is typically equal to c shut (1.11v)/15 m a. for example, a 1 m f capacitor on the shdn pin yields a 74ms ramp time. in short, this unique circuit block performs a current limit time-out function that latches off the regulator drive after a pre- defined time period. the time-out period selected is a function of system requirements including start-up and safe operating area. the shdn pin is internally clamped to typically 1.85v by q6 and r2. the comparator tied to the shdn pin has 100mv of typical hysteresis to provide noise immunity. the hysteresis is especially useful when using the shdn pin for thermal shutdown. restoring normal operation after the load current fault is cleared is accomplished in two ways. one option is to recycle the nominal 12v lt1575 supply voltage as long as an external bleed path for the shutdown pin capacitor is provided. the second option is to provide an active reset circuit that pulls the shdn pin below v ref . pulling the shdn pin below v ref turns off the 15 m a pull-up current source and reactivates the 5 m a pull-down. if the shdn pin is held below v ref during a fault condition, the regulator continues to operate in current limit into a short. this action requires being able to sink 15 m a from the shdn pin at less than 1v. the 5 m a pull-down current source and the 15 m a pull-up current source are designed low enough in value so that an external resistor divider network can drive the shdn pin to provide overvoltage protection or to provide thermal shutdown with the use of a thermistor in the divider network. diode-oring these functions to- gether is simple to accomplish and provides multiple functionality for one pin. if the current limit amplifier is not used, two choices present themselves. the simplest choice is to tie the ineg pin directly to the ipos pin. this action defeats current limit and provides the simplest, no frills circuit. an appli- cation in which the current limit amplifier is not used is where an extremely low dropout voltage must be achieved and the 50mv threshold voltage cannot be tolerated. however, a second available choice permits a user to provide short-circuit protection with no external sensing. this technique is activated by grounding the ineg pin. this action disables the current limit amplifier because schottky diode d1 clamps the amplifiers output and prevents q2 from pulling down the comp node. in addi- tion, schottky diode d2 turns off pull-down transistor q1. q1 is normally on and holds internal comparator comp3s output low. this comparator circuit, now enabled, moni- tors the gate pin and detects saturation at the positive rail. when a saturated condition is detected, comp3 activates the shutdown timer. once the time-out period occurs, the output is shut down and latched off. the operation of resetting the latch remains the same. note that this tech- nique does not limit the fet current during the time-out period. the output current is only limited by the input power supply and the input/output impedance. setting the timer to a short period in this mode of operation keeps the external mosfet within its soa (safe operating area) boundary and keeps the mosfets temperature rise under control. unique circuit design incorporated into the lt1575 allevi- ates all concerns about power supply sequencing. the issue of power supply sequencing is an important topic as the typical lt1575 application has inputs from two sepa- rate power supply voltages. if the typical 12v v in supply voltage is slow in ramping up, insufficient mosfet gate drive is present and therefore, the output voltage does not come up. if the v in supply voltage is present, but the typical 5v supply voltage tied to the ipos pin has not started yet, then the feedback loop wants to drive the gate pin to the positive v in rail. this would result in a
13 lt1575/lt1577 applicatio n s i n for m atio n wu u u very large current spike as soon as the 5v supply started to ramp up. however, undervoltage lockout circuit comp2, which monitors the ipos supply voltage, holds q3 on and pulls the comp pin low until the ipos voltage increases to greater than the internal 1.21 reference voltage. the undervoltage lockout circuit then smoothly releases the comp pin and allows the output voltage to come up in dropout from the input supply voltage. an additional benefit derived from the speed of the lt1575 feedback loop is that turn-on overshoot is virtually nonexistent in a properly compensated system. an additional circuit feature is built-in to the lt1575 fixed voltage versions. when the regulator circuit starts up, it must charge up the output capacitors. the output voltage typically tracks the input voltage supply as it ramps up with the difference in input/output voltage defined by the drop- out voltage. until the feedback loop comes into regulation, the circuit operation results in the gate pin being at the positive v in rail, which starts the timer at the shdn pin if the current limit amplifier is disabled. however, internal comparator comp4 monitors the input/output voltage differential. this comparator does not permit the shut- down timer to start until the differential voltage is greater than 500mv. this permits normal start-up to occur. one final benefit is derived in using an lt1575 fixed voltage version. todays highest performance micropro- cessors dictate that precision resistors must be used with currently available adjustable voltage regulators to meet the initial set point tolerance. the lt1575 fixed voltage versions incorporate the precision resistor divider into the ic and still maintain a 1% output voltage tolerance over temperature. thus, the lt1575 fixed voltage versions completely eliminate the requirement for precision resis- tors and this results in additional system cost savings. applications support linear technology invests an enormous amount of time, resources and technical expertise in understanding, de- signing and evaluating microprocessor power supply so- lutions for system designers. as processor speeds and power increase, the power supply challenges presented to the motherboard designer increase as well. application note 69, using the lt1575 linear regulator controller, has been written and serves as an extremely useful guide for this new family of ics. this application note covers topics including pc board layout for the lt1575/lt1577 family, mosfet selection criteria, external component selection (capacitors) and loop compensation. linear technology welcomes the opportunity to discuss, design, evaluate and optimize a microprocessor power supply solution with a customer. for additional information, consult the factory. ultrafast transient response 5v to 3.5v low dropout regulator with current limit and timer latchoff 1 2 3 4 8 7 6 5 shdn v in gnd out ipos ineg gate comp c2 1 m f c5 220 m f 5v gnd 1575/77 ta11 v out 3.5v 5a r2 5 w r3* 0.007 w r1 7.5k 12v lt1575-3.5 c4 1000pf c1 1 m f reset r3 is made from ?ree?pc board trace c6 = 24 1 m f x7r ceramic surface mount capacitors. place c6 in the microprocessor socket cavity * ** q2 vn2222l q1 irfz24 + c3 10pf c6** 24 m f typical applicatio n s n u
14 lt1575/lt1577 typical applicatio n s n u setting output voltage with the adjustable lt1575 fb 1575 ta03 r2 v out = 1.21v(1 + r2/r1) v out r1 using sense-less current limit c1 10 m f c t r3 10 w ipos shdn v cc 1575 ta04 v out q1 ineg gate shutdown time-out with reset overvoltage protection r3 100k r2 100k c2* 1575 ta09 *c2 = 15 m a(t)/1.11v t = shutdown latch-off time shdn q2 2n3904 reset 0v to 5v shdn 1575 ta10 v out r5 r6 v out(uth) = 1.21(r6/r5) + 5 m a(r6) v out(lth) = 1.11(r6/r5) ?15 m a(r6) shutdown time-out with reset basic thermal shutdown r1 100k c1* 1575 ta07 *c1 = 15 m a(t)/1.11v t = shutdown latchoff time shdn q1 vn2222l reset 0v to 5v shdn 1575 ta08 rt1 10k ntc 5v r4 549 w rt1 = dale nths-1206n02 thermally mount rt1 in close proximity to the external n-channel mosfet setting current limit ipos v cc r sense * *i lim = 50mv/r sense r sense = discrete shunt resistor or r sense = kelvin-sensed pc board trace activating current limit also activates the shdn pin timer 1575 ta05 v out q2 ineg gate setting current limit with foldback limiting ipos v cc r4 d1 1n4148 d2 1n4148 r5 10 w 1575 ta06 v out q3 ineg gate r6 1.2k
15 lt1575/lt1577 typical applicatio n s n u 1 2 3 4 8 7 6 5 + lt1575-1.5 r2 3.9 w r1 0.005 w r5 150 w r4 75 w r8 100 w r9 100 w v tt 1.5v r10 100 w r6 75 w r7 150 w r3 4.99k c5 1000pf c8 to c23 1 m f ceramic 0805 case c6 0.1 m f c7 0.1 m f v ref v ref q1 irfz24 c3 1 m f c4 10pf c2 0.22 m f reset 12v v in 3.3v c1 220 m f 6.3v shdn v in gnd out ipos ineg gate comp rx tx ? ? rx tx rx tx rx tx q4 q2 q3 q5 1575/77 ta12 142 total signal lines note: ltc recommends centrally locating the lt1575-1.5 output to minimize v tt distribution drops and using separate v ref generators at each bus end r11 100 w pentium ? ii processor gtl+ power supply generating 12v gate drive from a 5v power supply 1 2 3 4 8 7 6 5 lt1262 c1 0.22 m f c3 4.7 m f c8 390pf r1 2k 74hc14 d6 bat85 d3 bat85 c9 0.22 m f c7 100 m f 10v 1575/77 ta13 c6 10 m f 25v c5 100 m f 10v d1 1n5818 l1 33 m h c4 4.7 m f 12v 25ma 12v 25ma 12v 25ma v cc 4.75v to 5.5v v cc 4.75v to 5.5v v cc 4.75v to 5.5v c1 c1 + c2 c2 + shdn gnd v out v cc + + + + c11 0.22 m f c12 0.22 m f c10 0.22 m f c2 0.22 m f sw 2 1 3 lt1109cz-12 v out gnd + d2 bat85 d4 bat85 d5 bat85 5 pentium is a registered trademark of intel corporation.
16 lt1575/lt1577 typical applicatio n s n u 12v to 3.3v/9a (14a peak) hybrid regulator transient response to a 10a load step 50mv/div 200 m s/div 1575/77 ta17 + + + + + 1575/77 ta16 tg sw boost intv cc bg s + s extv cc c osc run/ss i th sfb sgnd v os 9 1 2 3 4 5 6 16 14 15 12 11 8 7 13 10 c4, 4.7 m f c5 0.1 m f d2 mbrs330t3 r8 15k r3 100 r4 100 c18 1000 m f 10v c20 1000 m f 10v c19 1000 m f 10v r6 0.0075 l1 4 m h c2, 1000pf v in ltc1435 c21, 10pf c22, 1000pf r2 1.21k 1% c1, 470pf r9 2k q1 irlz44 r1 2.1k, 1% v core 3.3v 1 2 3 4 8 7 6 5 pgnd d1, cmdsh-3 q3 q2 c16 1 m f c14 150 m f 16v c15 1 m f c17 1 m f 12v c11 150 m f 16v c12 150 m f 16v c13 150 m f 16v c3, 0.1 m f c9 1500pf r5 16.5k c10, 1000pf c8, 68pf c7, 0.1 m f r7 35.7k + c23 1 m f c6 0.1 m f 12v 1 m f x7r ceramic 0805 case 40 + + l1 = coiltronics ctx02-13199 q2, q3 = siliconix sud50n03-10 lt1575 shdn v in gnd out ipos ineg gate comp
17 lt1575/lt1577 typical applicatio n s n u 3.3v to 2.8v 100mv at 5.7a with sense-less current limit and timer latchoff + + 1 2 3 4 8 7 6 5 c2 330 m f 6.3v c3 680pf c7 10 m f c4 1000pf r1 4.7k r2 10 w c8 to c31* 1 m f q1 irl3303 v core 2.8v c5 22pf 1575/77 ta14 fault reset c6 0.1 m f 12v c1 330 m f 6.3v input 3.3v rtn + *x7r ceramic 0805 case lt1575-2.8 shdn v in gnd out ipos ineg gate comp n8 1197 0.100 0.010 (2.540 0.254) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.130 0.005 (3.302 0.127) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 0.125 (3.175) min 12 3 4 87 6 5 0.255 0.015* (6.477 0.381) 0.400* (10.160) max 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) n8 package 8-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) dimensions in inches (millimeters) unless otherwise noted. package descriptio n u
18 lt1575/lt1577 package descriptio n u dimensions in inches (millimeters) unless otherwise noted. s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 0996 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **
19 lt1575/lt1577 package descriptio n u dimensions in inches (millimeters) unless otherwise noted. information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. s package 16-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) 1 2 3 4 5 6 7 8 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.386 ?0.394* (9.804 ?10.008) 0.228 ?0.244 (5.791 ?6.197) 12 11 10 9 s16 0695 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **
20 lt1575/lt1577 ? linear technology corporation 1996 15757f lt/tp 0598 4k ? printed in the usa lt1577 split plane system typical applicatio n u + c2 330 m f 6.3v c3 0.33 m f c6 1500pf r2 3.9k r1 3.9 w r5 3.9 w c9 to c20* 1 m f q1 irfz24 v i/o 3.3v c5 10pf c8 1000pf r6 7.5k c7 10pf 1575/77 ta15 fault reset c4 1 m f 12v c1 330 m f 6.3v input 5v + q2 irfz24 *x7r ceramic 0805 case c21 to c44* 1 m f v core 2.8v 1 2 3 4 16 15 14 13 ipos1 ineg1 gate1 comp1 shdn1 v in1 gnd1 out-3.3 1/2 lt1577 5 6 7 8 12 11 10 9 ipos2 ineg2 gate2 comp2 shdn2 v in2 gnd2 out-2.8 1/2 lt1577 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com related parts part number description comments ltc1266 current mode, step-up/down switching regulator controller synchronous n- or p-channel fets, comparator/low battery detector ltc1392 micropower temperature, power supply and differential temperature to bits control voltage monitor ltc1430 high power step-down switching regulator controller voltage mode, 5v to 3.xxv at >10a ltc1435 high efficiency, low noise synchronous step-down current mode with wide input voltage range switching regulator ltc1553 digitally controlled synchronous switching regulator controller controller for pentium ii processor, buck conversion from 5v or 12v main power ltc1553l digitally controlled synchronous switching regulator controller controller for pentium ii processor, buck conversion from 5v main power lt1573 low dropout regulator driver drives low cost pnp transistor for high power, low dropout applications lt1580 7a, very low dropout linear regulator 0.54v dropout at 7a, fixed 2.5v out and adjustable lt1585-1.5 fixed 1.5v, 5a low dropout fast response regulator gtl+ regulator

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